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Junction Technology Group - Proceedings

November, 2005

Crunch Time Cometh for SDE Doping Engineering: Messages in ITRS05??.
  Michael Current, Frontier Semiconductor

Elimination of Poly-Si Gate Depletion for Sub-65nm CMOS Technologies by Excimer Laser Annealing
  Hiu Yung Wong, University of California, Berkeley

Flash-Assisted RTP for Advanced Ultra-Shallow Junctions
  P. J. Timans, Mattson Technology

Ni2Si and NiSi Formation by Low Temperature Soak and Spike RTPs
  Eun-Ha Kim, Stanford University

Ultra-Shallow Junctions for 65 nm Devices and Beyond
  Susan Felch, Applied Materials

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